1. Field of the Invention
The present invention relates to a central processor capable of accelerating program execution. More specifically, the invention relates to an architecture and scheme for interconnecting an otherwise conventional CPU core with a functional unit containing a lookup table and a reconfigurable combinational logic array in order to speed up the execution of general purpose, ordinary integer type operations.
2. Description of the Related Art
The Central Processing Unit (CPU) of a computer is responsible for executing programs, which are comprised of sequences of basic operations called instructions. The instructions need not be executed one at a time, or in the same order as specified by the program, as long as the actual sequence performed yields the same state changes (registers, memory, I/O) at any point in the program where this state can be observed. Most modern CPUs employ a number of techniques which allow the instruction execution mechanism to perform certain operations out-of-order, in parallel, in overlapping stages, speculatively, or not at all. Often the design of the instruction set is intimately intertwined with the execution model chosen, and places complex requirements on the programmer or programming language compiler for both correct program operation and optimal performance. This invention describes an alternative arrangement of a CPU core and a functional unit which provides a new strategy for program acceleration which succeeds in many instances where the current practice fails. It neither requires nor precludes the use of current state of the art techniques in the CPU core, and can be regarded as a complementary resource for enhancing processor performance.